Details

Title: Timing performance of nanometer digital circuits under process variations
Creators: Champac Victor; Gervacio Jose Garcia
Imprint: Cham, Switzerland: Springer, 2018
Collection: Электронные книги зарубежных издательств; Общая коллекция
Subjects: Радиосхемы; Наноструктурные материалы; Микроэлектронные схемы интегральные
UDC: 621.396.6.061; 620.22-022.53; 621.3.049.77
Document type: Other
File type: Other
Language: English
Rights: Доступ по паролю из сети Интернет (чтение, печать)
Record key: RU\SPSTU\edoc\60207

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Annotation

This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level “design hints” are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.

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