An object of study is anunary DAC. A overview of weighting elements switching sequences for unary DACs is presented. Anarrangement formalization of the known switching sequencesis performed. A mathematical model of anunary DAC taking into account a systematic error is introduced. A modeling of static characteristics is conducted. Some tendencies are concluded from the modeling results. Moreover, preferable weighting elementswitching sequencesis detected in order to reduce static nonlinearity.New switching sequences based on detected tendencies is proposed. A circuit of an 8-bit segmented DAC is designed forUMC L180 CMOS Mixed-Mode/RF technology. A DAC operation modeling taking into account parasitic elements of a topology is performed. The modeling shows that the parasitic elements don't effect significantly on the DAC static nonlinearity.