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Object of study is the digital signal-processing path of a delta-sigma DAC and architectural and RTL-level methods for reducing switching activity. The aim is to develop and verify a low-power delta-sigma DAC digital front-end based on a five-stage half-band interpolation chain, a MASH 1-1-1 modulator, and a DWA block. The following tasks were solved: Analysis of delta-sigma DAC architectures and interpolation methods; Development of a five-stage multiplierless half-band FIR interpolation chain using CSD coefficient representation and CSE optimization; Design of a MASH 1-1-1 delta-sigma modulator and a DWA-based unit-element selection block. As a result of the study, a complete digital front-end of a delta-sigma DAC was developed, including the interpolation chain, the noise-shaping modulator, and the dynamic element matching logic; the methods of polyphase half-band filtering, CSD coefficient encoding, common subexpression elimination, clock-enable gating, operand isolation, SAIF-based switching-activity analysis, and transistor-level simulation of DAC-related circuitry were used. As a result of the study, the proposed interpolation chain was shown to reduce switching activity compared with a functionally equivalent multiplier-based implementation: the reduction reaches 70–77% for the first half-band stage, and SAIF-based post-implementation power estimation in Vivado shows an overall dynamic-power reduction of approximately 27–34% for the complete filter chain. System-level modeling of the developed MASH 1-1-1 modulator demonstrates a peak SNDR of 79.68 dB. The novelty of the work lies in combining CSD/CSE-optimized half-band interpolation, CE control, operand isolation, and DWA logic in a single delta-sigma DAC digital front-end. The results can be applied in energy-efficient mixed-signal systems and IoT-oriented transmitter architectures. The work used MATLAB/Simulink for behavioral modeling and signal analysis, Icarus Verilog and ModelSim for RTL simulation, Xilinx Vivado 2020.2 for synthesis, implementation, and SAIF-based dynamic-power estimation on the Zynq-7020 platform, Cadence Virtuoso for transistor-level DAC simulation, and Verilog-2001 for digital RTL description.